1. Field of the Invention
This invention relates in general to a dynamic random access memory device and, more particularly, to a dynamic random access memory which makes it possible to perform more effective aging.
2. Description of the Background Art
FIG. 4 is a block diagram showing an example of a conventional dynamic random access memory device, referred to hereinafter as DRAM. Referring to FIG. 4, this DRAM includes a memory array 58 composed of memory cells for storing data signals, an address buffer 54 for receiving address signals for selecting the memory cells, a row decoder 55 and a column decoder 56 for decoding the address signals, and a sense amplifier 63 connected to the memory array 58 and adapted for amplifying and reading signals stored in the memory cells. An input buffer 59 to which data signals D.sub.in are entered and an output buffer 60 from which data signals D.sub.out are outputted are connected to the memory array 58 via an I/O gate 57.
The address buffer 54 is connected for receiving external address signals ext. A0 to A9 or internal address signals Q0 to Q8 generated from a refresh counter 53. A refresh controller 52 is responsive to changing timing of RAS and CAS signals applied to a clock generator 51 to drive a refresh counter 53.
In addition to the above components, this DRAM further includes a cell plate voltage generator 71 for generating a voltage Vm to be applied to a cell plate of each memory cell, and a switching circuit 70 connected to receive a voltage Vm and a ground potential Vss and adapted for selectively outputting one of these voltages as a cell plate voltage Vcp. The switching circuit 70 operates in response to a control signal .phi.1. The signal .phi.1 is outputted by a selection signal detecting circuit 30 when a voltage higher than the supply voltage V.sub.cc is applied to any one of the address terminals. In another example, the signal .phi.1 is externally applied through a spare terminal without using the selection signal detecting circuit 30. However, if the DRAM has no spare terminal, the signal .phi.1 cannot be directly applied, since no terminal should be newly added for aging. It is noted that an external source voltage Vcc and the external ground voltage Vss are applied to this DRAM via terminals 61 and 62, respectively.
FIG. 5 is a circuit diagram showing a part of the memory cell array 58 and the switching circuit 70 shown in FIG. 4. The circuit shown in FIG. 5 may be seen in the Japanese Patent Laying-Open No. 252598/1987.
Referring to FIG. 5, the memory array 58 includes a large number of memory cells 8 each connected between a bit line 1 and a word line 2. Each memory cell includes an NMOS transistor 7 for switching and a capacitor 5 for holding the data signal voltage. Each capacitor 5 has its one electrode 5a connected for receiving the cell plate voltage Vcp from the switching circuit 70 and the other electrode 5b connected to the transistor 7. The capacitor 5 includes an insulator 5c between its two electrodes 5a and 5b. The transistor 7 is connected between the bit line 1 and the other electrode 5b of the capacitor and has its gate connected to the word line 2.
The switching circuit 70 includes a transmission gate 13 connected for receiving the voltage Vm from the cell plate voltage generator 71 and a transmission gate 15 connected for receiving the ground voltage Vss. The transmission gate 13 includes a parallel connection of a PMOS transistor 12a and an NMOS transistor 12b. Similarly, the transmission gate 15 includes a parallel connection of a PMOS transistor 14a and an NMOS transistor 14b. Each of the transistors 12a and 14b has its gate connected to receive a control signal .phi.1 and each of the transistors 12b and 14a has its gate connected to receive an inverted control signal .phi.1. The control signals .phi.1 and .phi.1 are supplied from a control circuit not shown in FIG. 5. The voltage Vm has a value equal to (Vcc-Vss)/2.
During the usual read out or write mode, 5 volts of Vcc and 0 volt of Vss are supplied. One of the word lines 2 is brought to a high level by the row decoder 55 shown in FIG. 4, so that the associated transistor 7 is turned on. During the read out mode, the charges of data signal stored in the capacitor 5 are supplied to the associated bit line 1 via transistor 7. The sense amplifier 63 shown in FIG. 4 amplifies minute voltage changes in the bit line 1. The amplified signals are outputted via I/O gate 57 and the output buffer 60. During the write mode, data input signals applied from outside are transmitted to a selected one of bit lines 1 via input buffer 59 and I/O gate 57. The signal voltage on the bit line 1 is supplied to the other electrode 5b of the capacitors via the transistor 7 turned on by the row decoder 55.
During the above described usual read out and write modes, the voltage Vm (=(Vcc-Vss)/2) is supplied to the other electrode 5a of the capacitor 5 as the cell plate voltage Vcp. That is, the transmission gate 13 is turned on responsive to the signal .phi.1 to transmit the voltage Vm to the one electrode 5a of the capacitor in each memory cell 8.
As a rule, an aging test is performed before shipping of the DRAM. Aging is a test in which a device is moderately stressed for a certain period until its properties are stabilized in a constant state. In aging DRAMs, insulating properties of the insulator 5c in the capacitor 5 included in the memory cell 8 shown in FIG. 5 are ascertained.
FIG. 6 shows a timing chart for illustrating the aging operation in the circuit shown in FIG. 5. In the aging mode, 7 volts of Vcc and 0 volt of Vss are supplied. Referring to FIGS. 5 and 6, the transmission gate 15 is turned on responsive to a low level signal .phi.1 and a high level signal .phi.1 generated by an inverter. Thus, the ground voltage Vss is supplied to the one electrode 5a of the capacitor via transmission gate 15 as the cell plate voltage Vcp. Simultaneously, an input data signal "1" for aging is supplied to the input buffer 59 shown in FIG. 4 for bringing a selected bit line 1 to the level of the source voltage Vcc. As a result, a higher voltage Vh (=Vcc-Vss) is applied across the two electrodes 5a and 5b of the capacitor 5.
After the impression of this high voltage Vh is continued for a predetermined time, the usual write and read out operations of the DRAM are executed. When the insulator 5c in the capacitor 5 is free of defects, the written data signals are read out correctly. Conversely, when the insulator 5c in the capacitor is defective, correct data signal cannot be read out. The insulating properties of the insulator 5c of the capacitor included in the memory cell can be ascertained by the above described aging test.
In the above example, the ground voltage Vss is used as the cell plate voltage Vcp. However, the source voltage Vcc may also be used as the cell plate voltage. In this case, however, a data signal "0" is supplied to the input buffer 59 shown in FIG. 4 in place of "1" so that a selected one of the bit lines 1 is brought to the level of the ground voltage Vss. Hence, a higher voltage of opposite polarity -Vh is applied across the two electrodes 5a and 5b of the capacitor 5.
As is apparent from the foregoing, it is noted that no terminal is provided in the DRAM for directly applying the cell plate voltage V.sub.cp from outside. The reason for this is that an additional terminal must be provided for externally and directly applying the voltage V.sub.cp, which is not preferable.
In general, for ascertaining the insulating properties of an insulator, it is necessary to apply voltages having opposite polarities. This may be seen from a thesis publicized by Y. OHJI et al in a Symposium of International Reliability Physics held in 1987 and entitled "RELIABILITY OF NANO-METER THICK MULTI-LAYER DIELECTRIC FILMS ON POLY-CRYSTALLINE SILICON". However, in the conventional DRAMs, only a single polarity of test voltage either Vh or -Vh can be applied to the insulator 5c of the capacitor 5 in the memory cell 8 during the aging test, so that it has not been possible to carry out a complete aging test for DRAMs.
A prior art having particular pertinence to the present invention may be seen in a U.S. Pat. No. 4,527,254 entitled "DYNAMIC RANDOM ACCESS MEMORY HAVING SEPARATED V.sub.DD PADS FOR IMPROVED BURN- IN", issued to Ryan et al on Jul. 2, 1985. In this prior art, an external voltage higher than the source voltage is applied to the DRAM during aging to shorten the time involved in aging. However, nothing is said of the polarity of the applied voltage.
An example of prior art having particular pertinence to the present invention is the Japanese Patent Laying-Open No. 232155/1987. In this prior art, a test voltage generator adapted for generating a voltage not less than the source voltage is included in the DRAM so that the voltage applied during aging has only one polarity.
Besides this prior art example, the Japanese Patent Laying-Open No. 192998/1987 also shows another example in which the voltage impressed during aging has only one polarity.